1. Field of the Invention
The present invention generally relates to an insulated gate bipolar transistor, and in particular, relates to a vertical insulated gate bipolar transistor and a method of manufacturing the same.
2. The Prior Arts
An IGBT (Insulated Gate Bipolar Transistor) features a MOS gate for high impedance voltage-control and bipolar conduction for reducing the drift on-state resistance (through ‘conductivity modulation’). It can be seen as a successful combination between a Power MOSFET and a bipolar transistor. The IGBT operates commonly in the range of 500 V to 8 kV with current capability ranging from a few hundred mA for Power ICs to 5000 A for applications in HVDC or traction. Their strongest market is in motor control with voltage ratings from 500 V to 1.2 kV and current capability from 5 A to 500 A.
Function of the structure of the drift region and the anode structure and in particular the extension of the depletion region into the drift region at breakdown, the IGBTs can be split into three categories (a) Punch Trough (PT); (b) NON Punch-Through (NPT); and (c) Soft Punch Through (SPT), also known as Field Stop IGBT (FS IGBT) or Light Punch Through IGBT (LPT IGBT).
(a) PT IGBT
The main characteristics of the PT IGBT are that the depletion region fills the whole of the drift region in the blocking mode at or before avalanche breakdown occurs. To stop the depletion region reaching the p+ anode region, a buffer layer of the same conductivity type as that of the drift region but more highly doped is inserted between the drift region and the p+ anode layer. For devices rated at 600V, 1.2 kV and 1.7 kV the punch-through (PT) device is based on an epitaxial drift region/buffer grown on a highly doped p+ substrate. While the drift layer is very thin and can potentially give benefits in the on-state and cutting the turn-off tail, the device requires electron irradiation or well controlled local ion irradiation with high energy implants to increase its switching speed and hence reduce its transient losses.
(b) NPT IGBT
The “Non Punch Through” NPT-IGBT has a homogeneous substrate material (float zone) as the drift region. For an n-channel device (virtually all the IGBTs today are n-channel devices), the drift region is of n-type. Its doping is the lowest of all regions. The exact level and the length are determined to withstand the rated breakdown voltage. The p+ anode is usually built as a thin and relatively lowly doped layer (still considerably more highly doped than the drift region) after most of the fabrication steps to build the top of the device (e.g. diffusions, implantations, gate oxidation, etc) are carried out. The depletion region at breakdown does not fill the entire drift region. A protective margin of a drift region, typically 20-40 microns is left between the end of the depletion region at breakdown and the edge of the p+ anode layer. The NPT IGBT has shown increased robustness during short-circuit conditions and a more desirable plasma distribution in the on-state which overall cuts the switching losses in spite of its increased drift length. This is because in NPT-IGBTs the bipolar gain is adjusted via the injection efficiency of the anode layer (the emitter of the pnp transistor) rather than the base transport factor (which is dependent on the lifetime of the carriers) as it is the case in PT IGBTs. As a result the charge distribution in NPT-IGBTs is more uniform with a lower peak value at the anode side, which in turn results in a less lossy turn-off. However, as already mentioned, the PT structure has the potential to lower the on-state losses on account of its reduced drift length.
(c) SPT IGBT
The SPT IGBT combines the advantages of the two structures, PT and NPT IGBTs. It has been proposed a few years ago and is called Soft Punch-Through (SPT), Field Stop (FS), or Light Punch-Through (LPT).
The SPT IGBT is based on having a punch-through type drift region (similarly to that of the PT IGBT) but unlike in the PT IGBT, it features a lightly doped buffer and a lightly doped and transparent anode. The idea is to adjust the plasma (i.e. excess charge) in the drift region by controlling the injection efficiency of the anode junction rather than the base transport factor of the bipolar transistor. The buffer layer no longer suppresses the hole injection as it is relatively lowly doped, but its role is only to stop the parasitic punch-through breakdown by preventing the depletion region (the high electric field) to reach the anode junction. Its doping should be low enough not to influence the hole injection but high enough to stop the electric field. Thus its role is to make sure that the punch-through breakdown does not take place before avalanche in the drift region. The buffer can also be designed that the two effects (i.e. punch-through and avalanche) take place almost concomitantly. The name of soft punch through comes from the softer characteristics obtained during the switching (when compared to a PT structure). The use of the lightly doped buffer offers a ‘soft’ extension of the depletion region inside this layer as opposed to an abrupt stop which can generate noise, overshoots and/or EMI issues.
FIG. 1a shows a schematic view of a PT IGBT according to the prior art. FIG. 1b shows a schematic view of a NPT IGBT according to the prior art. And FIG. 1c shows a schematic view of a SPT IGBT according to the prior art. As shown in FIG. 1a to FIG. 1c, the three structures, PT IGBT, NPT IGBT and SPT IGBTs are shown. The dimensions are example for a 1.2 kV rating. It can be seen that PT substrate (wafer) is of p+ doping while the n buffer and the n− drift region are grown epitaxially. The trade-off between on-state and turn-off losses is adjusted most commonly by electron irradiation of the entire n-drift region. In NPT structure the substrate (wafer) is of n− drift region and the trade-off between on-state and turn-off losses is adjusted via the injection efficiency of the p+ anode/n− drift p-n junction. For this the p+ anode is relatively lowly doped (e.g. 1×1017 cm−3) and is relatively thin (e.g. 1 micron). The NPT drift region is however thicker than that of the PT device. In SPT device, the n− drift region is the substrate (wafer), but is as thin as that of a PT device. The on-state and turn-off losses are adjusted via the injection efficiency of the p+ anode/n− buffer p-n junction.
TABLE 1 shows the relative qualitative performance of the three devices. In most categories SPT is a winning solution.
TABLE 1StructurePT - IGBTNPT - IGBTSPI - IGBTDrift layer thicknessthinthickThinWafer type (for 600 VEpitaxialFloat zone (FZ)Floatand 1.2 kV)Zone (FZ)Buffer LayerThick and highlyN/AThin anddopedlowly dopedP+ anode injectorThick andThin andThin andhighlyrelativelyrelativelydoped (wholelowly dopedlowly dopedsubstrate)Bipolar gainLifetimeInjectionInjectioncontrolkillingefficiencyefficiencyOn-state losseslowmediumlowSwitching losseshighmediumlowTurn-off tailshortlongshortVoltage overshoot (inhighlowLowsome applications)Temperaturenegative (mostly)positivepositivecoefficientSCSOA (short circuitmediumlargelargeconditions)RBSOA (reverse biasnarrowlargeLargeconditions)
The adjustment of injection efficiency by using a lowly doped transparent anode in SPT device is very similar to the concept employed in the NPT IGBT. However unlike in NPT IGBT, the drift region is significantly thinner. As a result, the charge distribution in the SPT IGBT is more favourable, allowing for a ‘closer to optimal’ loss profile. It is already known that a significant advantage can be obtained by lowering the charge at the anode side (which is responsible for the long turn-off tail of the IGBT) and maintaining un-affected or even increasing the excess charge at the other side of the drift region, in order to minimize the on-state losses. The control of the anode injection efficiency while maintaining a high carrier lifetime in the drift region achieves exactly this. The charge no longer deeps in the middle as it is the case with uniform lifetime killing, which leads to poor trade-off between on-state performance and switching losses, but the charge is only lowered at the anode side which leads to an almost flat profile along the drift region (see FIG. 3). As a result, in the SPT IGBT both the on-state losses and switching losses can be minimized. The SPT IGBT turn-off is significantly faster than both the PT and NPT IGBT reducing the switching losses by 10-30%. Given its short drift length, the SPT-IGBT can also additionally reduce the on-state losses by 10-20% compared to state-of-the-art NPT IGBTs.
Function of the geometrical arrangement of the MOS channel, the IGBTs can be split into two categories. In DMOS IGBTs, the channel is horizontal while in the Trench IGBT the channel is vertical. The trench technology has considerable advantages over the DMOS technology, such as higher electron injection at the top of the n− drift region, more natural, one-dimensional current flow, no parasitic JFET effect, higher channel density etc. FIG. 1 shows the three structures NPT IGBT, PT IGBT and SPT IGBT in DMOS technology. All these structures can also employ trench gate structures. For example an SPT IGBT in trench technology is shown in FIG. 2. Not only that the trench improves the channel density (thus minimizing the on-state voltage drop on the channel) but its strong PIN diode effect (injection enhanced effect) increases the charge at the cathode side of the drift region, thus leading to an even lower on-state without compromising the turn-off speed. FIG. 3 shows the carrier distribution in a NPT IGBT (based on transparent anode), a PT IGBT (based on uniform lifetime killing), a DMOS SPT IGBT and a Trench SPT IGBT. The use of trench coupled with the SPT structure allows an almost ideal plasma distribution with a relatively low peak at the anode side and slightly increased peak at the cathode side. In addition the trench also helps to reduce the latch-up susceptibility and suppress the parasitic JFET effect. Given its advantageous carrier profile, the SPT structure offers a clearly superior trade-off between on-state and turn-off energy losses. The graph in FIG. 4 shows schematically the trade-off between PT, NPT & SPT DMOS and Trench IGBTs for 1.2 kV. Similar graphs can be shown for other rated voltages such as 600 V, 1.7 kV, 3.3 kV, 4.5 kV or 6.5 kV.
From the description of state-of-the-art in IGBTs given above, it is clear that the SPT IGBT offers significantly better performance than both NPT and PT IGBT. However the SPT IGBT employs very thin wafers (e.g. 100 microns) which are very difficult to handle during fabrication. Also, the use of special handle wafers and updating of equipment to allow processing of such wafers lead to a considerable cost increase. At the same time the formation of the lightly doped n− buffer layer and the p+ anode are very difficult steps to control, as these need to be done after the formation of virtually all the layers at the top of the device. As a result, the n− buffer layer and the p− anode are done using ‘cold’ processes with temperatures below 500° C.
On the other hand, the PT structure is convenient and relatively cheap to make and does not require handling of thin wafers. However the use of electron irradiation leads to poorer overall electrical performance. In addition, the electron irradiation affects the threshold voltage of the device. An extra annealing step to recover the threshold voltage is necessary. Nevertheless the variation in the threshold voltage from wafer to wafer and batch to batch remains relatively high and the overall yield in general is affected.
In U.S. Pat. No. 7,301,220, a technique is proposed to adjust the injection efficiency by introducing highly doped n+ islands in the n buffer layer of a lateral IGBT (FIG. 5). This technique is conceived for lateral structures to be used in integrated circuits. The n+ islands are formed during the fabrication of the cathode n+ and CMOS n+ source and drain layers.